Design and Implementation of Low Power CMOS Flash ADC in Cadence Tool | Original Article
Analog to digital converter is a critical device, has huge applications in today’s digital world. This paper describes the design of FLASH ADC using 180nm CMOS technology. The FLASH has highest speed among all the other ADCs due to its parallelism. This consists of series of comparators which give thermometer coded outputs which is converted to the digital form by an encoder. The main disadvantage of this ADC is its power consumption. Comparators are the power hungry circuits whose power dissipation is reduced. The main aim of this paper is to design low power FLASH type ADC. Pre-layout and post layout simulation is done using cadence virtuoso analog design environment. The comparators output is encoded using an encoder designed with full adders to reduce the number of transistors.