High Performance and Scalable on-chip Bus with Thread Extension using Open Core Protocol | Original Article
In recent technology most of the core function need an on-chip bus having inter-operability interface irrespective of the core features. The issues that relate to SOC are communication between different core, integration of different clocked domain, increase in performance of system and requirement of a standard protocol interface. This paper presents the open core protocol (OCP) interface implementation with features simple basic OCP signals, burst OCP signals, tag OCP signals. The OCP interface is investigated with two different core systems. The implementation is designed with Xilinx ISE tool in verilog HDL language and verification of OCP interface is carried out.