VLSI Implementation of High Speed FFT Processor | Original Article
In today’s wireless technology, use of FFT processor for processing the data adds more advantages like high speed and less power consumption and reduction in circuit complexity etc. Hence to meet the real time requirements it is very much necessary to design high performance FFT architecture. Here attempt is made to design, an alternative architecture for 16 point radix-2 based decimation in frequency (DIF), fast fourier transform (FFT) processor by combining two 8 point FFT’s successfully. The new 16 point DIF-FFT architecture design is simulated by using ModelSim and synthesized by Xilinx ISE project navigator. The synthesis reports of the proposed architectures are compared with the existing architectures. Finally comparison reports shows that the proposed 16 point DIF-FFT architecture is more efficient in speed, power and memory utilization. Hence the proposed architecture can be used for any application that requires low power and high speed operation.