An Analysis on Various Calibration Techniques For High Performance Sar A/D Converter Design |
Modem portable and wireless applications are driving analog-to-digitalconverters (ADCs) design towards higher resolution and data rates withdramatically low power in scaled CMOS technology. Pipelined ADCs have beenfacing significant challenges with technology scaling since accurate residueamplification in each pipelined stage based on op-amplifier's property isrequired. Successive-Approximation-Register (SAR) ADC can benefits from thescaled CMOS because it does not need amplifier and most of the parts, switchedcapacitors and comparator, are digitally operation. Charge redistribution basedcapacitor DAC (CDAC) is widely used for SAR ADCs because of its superiorresponse to resister DAC (RDAC). SAR ADC has become a main stream inapplication for several tens of megahertz and moderate resolution region due tothe advantage of power and area efficiencies. The most design efforts for theCDAC based SAR ADC have been put on the comparator and the CDAC. This paper presents the design of three high-performancesuccessive-approximation-register (SAR) analog-to-digital converters (ADCs)using distinct digital background calibration techniques under the framework ofa generalized code-domain linear equalizer. These digital calibrationtechniques effectively and efficiently remove the static mismatch errors in theanalog-todigital (A/D) conversion. They enable aggressive scaling of thecapacitive digital-to-analog converter (DAC), which also serves as samplingcapacitor, to the kT/C limit. As a result, outstandingconversion linearity, high signal-to-noise ratio (SNR), high conversion speed,robustness, superb energy efficiency, and minimal chip-area are accomplishedsimultaneously.