Simulation and Fault Analysis of HVDC Line Protection using C.B. | Original Article
Recently, studies on HVDC circuit breaker (CB) prototypes have shown successful take a look at results. Nevertheless, effective and reliable solutions relating to massive fault energy during dc fault interruption have not nevertheless been commercialized, and dc current breaking topologies on ways of achieving artificial zero should be somewhat modified. As another, one possible resolution is to mix fault current limiting technologies with dc breaking topologies. In this paper we studied the applying of resistive superconducting fault current limiters (SFCLs) on various sorts of HVDC CB so as to estimate the consequences of combining fault current limiters and conventional dc breakers. For the simulation works, four sorts of dc breaker topologies were modeled, as well as a mechanical CB using black-box arc model, a passive resonance CB (PRCB), an inverse current injection CB, and a hybrid HVDC CB. In addition, a resistive SFCL was simulated and added to the dc breakers to verify its interruption characteristic and distributed energy across HVDC CB. From the simulation results, we have a tendency to found that the utmost fault current, interruption time, and dissipated energy stress on the HVDC CB might be decreased by applying SFCL. In addition, it had been observed that, among four types of HVDC CB, PRCB with SFCL exhibited the best observable enhancement.