Study of Asynchronous Analog-To-Digital Converter In Cad Graphics

ADC (Analog to Digital Converter) is one of the main components in digital signal processing systems. As the name implies the ADC is used to convert analog signals (continuous) into digital signal (discrete). Digitizing process done through sampling and quantization. Sampling rate will determine the sample size of unity of time (seconds). Quantization resolution determines the number of bits that are used to encode the value of each sample. With the continued development of high-speed digital electronic devices that source data is analog data, the role of the ADC continues to rise. The need for ADC are high now, and must have the following specifications; power consumption and low voltage, has high conversion speed, small delay, and output bits are great. With these specifications Asynchronous ADC is one of the devices that are still widely developed in that direction. Preparation techniques with unipolar transistors is known as VLSI systems (Very Large Scale Integration) by combining the power engineering and semiconductor companies in the development of a prototype chip VLSI design with CMOS technology (Complementary Metal Oxide Semiconductor, Inc.) for integrated applications (digital equipment) [1,2]. CMOS technology can also be used to design analog and RF circuits CHIP so many complex systems developed with the help of CAD (Computer Aided Design). Development of integrated component technologies (VLSI) grows progressively smaller size (currently upon 90nm technology) and enabling the development ofSOC (System On Chip) for multimedia equipment, egdigital camera, Mobile, Player, Networking and others. The purpose of this study to obtain the ADC designthat has high speed, high accuracy and low powerdissipation. In high-speed ADC is typically used toconvert the video signal. In this study, expected to beable to design and implement a series of componentsinto the prototype A-3- bits ADC component eg op-amps, comparators, digital logic, DACs (switchcapacitor).

Asynchronous sampling ADC and a data type withNyquis. ADC is a new variant of this type of ADC.When viewed from the way it works is actually amodification of the SAR [5] type ADC. Block diagram ofA-ADC, as shown figure 1.

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ADC architecture that is designed in this research is the development of asynchronous ADC architecture (A-ADC), the main design on Switch capacitor [7]. Input analog signals will be captured by the SC to be compared with the signal or reference voltage. In addition to the input signal SC will also get a signal from the decoder which is also a comparison of the digital data signal from the previous signal. In the figure 1 can see that the signal output from the DAC would go into the OP-AMP and the comparator, which will be processed by these blocks and further into the data '1 'and '0' as the driver of the digital logic. Output signal from digital logic block is the data out in the form of digital data and time.

The function of the op-amp in the ADC is used to process the sample and hold (SHA) and multiplying, the requirement specifications of the op-amp in the ADC are [2]: At figure 2 op-amp OTA circuit, differential amplifier (Ml-4) provides two input flip and did not reverse the cause noise and offset. Strengthening (high gam M6-7) is almost similar to the gates of notes when the op-amp drives the low load stage is then followed by a buffer (buffer), flow together (EVI5) are provided by the current mirror circuit |"4"|. Ideal op-amp characteristics, reinforcement of the infinite open mode (AOL = strengthening the closedmode (Buffer = ACL) = 1, infinite input impedance output impedance is almost equal 0 strengthening bandwidth (GBW = a large Fout = AV (V +-V-). Av used with designs on strengthening the open mode (Aol)[2]. All of op-amp has a restriction on its operating voltagerange. C'MIR limits (common input mode range) is theborder of the scale range of each mput op-amp. outsidethese limits cause output distortion or truncated. Function of current mirror as bias current source forcomponents for controlling or mos can also drive or as acurrent mirror with a current source control. In figure 2 two stage op-amp trans-conductance can beanalyzed as follows: Gain of stage 1 gds = parameter trans-conductance drain to source = parameter channel length modulation

The template Function of comparator as input signalcomparator with reference tension (ADC), output ofcomparator is binary logic 0 or 1. at Figure 3 precisioncomparator block diagram. For unit pre-amp is applied bytype differential and in set for capacitance input with activeload, unit decision is functioning comparator heart tochange from current to tension, Besides as positivefeedback by adding component together, applied to shiftlevel hystersis as well as depressing noise. Prop unit(buffer) functioning as medium level tension to binary logic(0,1).

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Functioning decision unit changes level current to level voltage, hence big of output voltage depended measure M7- M10, and functioning M11 as hysteresis shifter or eliminate noise[4] If Io+ bigger of value Io- so M7, M9 to condition ON, and M8,M10 to condition OFF, if value β7 = β10 = βA and β8= β9 = βB and Vo-= 0 so :

Digital logic is a block that serves to process the inputsignal from the Op-Amp to be used as digital data. Thiscomponent consists of counters, decoders and timers. Counter will work based on the input or data from thecomparator. When an input '1 'it will increase (INC) and ifthe input '0' then will decrease (DEC). The output of thiscounter will be two parts, first as a timer and the second asthe data out. Out the data size and time depending on thedata output of the comparator.

DAC is componen for feedback is cooperating withdecoder and has errors corection which good for reducingmistake of conversion that is possibly happened. Signaland or this digital data later will be interfaced to DAC to beprocessed again and becomes perfect digital data.

From the design of each unit can be simulated. The resultsof each simulation can be described depending on thecircuit being simulated. OP-AMP circuits Resultsimulations like Figure 6.

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Calculation of simulation with Kn=175μA/V and Kp = 60μA/V), happened difference with result of simulation equal to 3,62dB if compared to first simulation. At precision comparator unit (ADC), simulation emphasized at comparator offset By providing an input DC voltage Vin with a 1.65-V and Vin + variable DC input from 0V to 3.3 V, showed changes in output (Fout) with set point at 1.65 V. When Vin 0V to 1.65V then Fout = 0V (0) and then when Vin moved from 1.65 V to 3.3 V, so Fout = 3.3 V (1) In digital logic units, which are critical to the counter because it blocks all incoming signals and processed at this Counter. The simulation results as Figure 8. By giving input frequency of 100 MHz can be produced bythe counter to count forward or backward according tocondition of device. Data out will be converted by decoder and outputs a binarysignal will be input to feedback unit, as figure 9. Thissignals will be a reference to Error Correction .

This Asynchronous ADC has been designed in theschematic (circuit). The result still in the simulation andearns at a speed of frequency 100 MHZ. Applicationapplied for video signal. ADC designed hardly considersresolution and speed that is later can be applied orcoupled with equipments of other multimedia orequipments especially for high-speed camera.

[1] B. S. Song, La Jolla, and Gilman,” Design CMOSAnalog-to-Digital Converter,” ECE264C,International WorkShop in University of California,San Diego,2007 [2] Cheongyuen B.T ,” Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS,”No.67 UCB/EECS, 22 May 2008. [3] E. Allier, J. Goulier, G. Sicard, M. Renaudin, “A120 nm Low Power Asynchronous ADC”, ISLPED2005

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[4] Eri Prasetyo, Hamzah Afandi, Dominique Ginhac and M. Paindavoine ,”A 8-bits Pipeline ADC Design For High Speed Camera Application,”IES 2007, ITS 2007 [5] Eugenio Culurciello, Andreas G. Andreou,” An 8-bit 800-uW 1.23- MS/s Successive Approximation ADC in SOI CMOS”, IEEE, Transaction on Circuits and System-II; Vol.53, No.9, September 2006 [6] J. Baker and D. E. Boyce,” CMOS Circuit Design, Layout and Simulation.” IEEE Press on Microelectronic Systems, 1998 [7] M. Trakimas, S. Sonkusale, Tufts University, “A 0,8 V Asynchronou ADC Energy Constrained Sensing Applications” IEEE, CCIC, pp. 173-176. Januari 2008 [8] Seung-Chul Lee, Young-Deuk Jeon, and Jong-Kee Kwon,”A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique,” ETRI Journal, Volume 29, Number 3, June 2007 [9] Shuo-Wei Michael Chen, Student Member, IEEE, and Robert W. Brodersen, Fellow “A6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-mCMOS” IEEE journal of solid state circuits, vol. 41 no. 12, Desember 2006 [10] Theja Tulabandhula, Theja Tulabandhula, Yujendra Mitikiri, “A 20MS/s 5.6 mW 6b asynchronous ADC in 0.6um CMOS” IEEE VLSI Design, 22nd, pp. 111-116, 2009 [11] W. Li, K.L. Shepard, Y. P. Tsividis, ”Continous Time Digital Signal”, International Symposium on Asynchronous Circuits and Systems, 2005 [12] www.mentor.com/ams.html,2008 “Parameter Ruler Design CMOS AMS 0,35um,” Mentor Graphics Corporation