Reconfigurable Embedded Systems: a Systematic Design Tools & Architecture

The reconfigurable hardware was used to construct high performance computational structures, whereas the microprocessor controlled when and how often a new computational structure was initiated. At the time, the F+V structure computer was intended for scientific computational problems that were out of reach for conventional microprocessors. However, it did not reach into commercial products as reconfigurable hardware was a hardly explored field and as the performance of conventional microprocessors was constantly growing and simply considered sufficient. Today, the field of reconfigurable computing is compelling as a complement to embedded systems that contain numerous application specific integrated circuits (ASICs). Since 1960, reconfigurable architectures have evolved and there is a consensus that they are a promising solution to bridge the gap between ASIC performance and processor flexibility (Guohuan, et. al., Dec. 2009). However, customary architectures such as field programmable gate arrays (FPGAs) cannot match energy and area efficiency of ASICs. It is because FPGAs are built as arrays of interconnected functional blocks operating at bit-level, whereas many signal processing algorithms utilize word-level arithmetic’s. Word-level arithmetic’s implemented on architectures that have bit-level functional blocks, because an overhead in required hardware area and energy consumed during operation. In order to reduce this weakness, researchers have suggested new types of reconfigurable architectures with coarse-grained functional blocks. The design space for these coarse-grained architectures is neither sufficiently explored nor well understood when it comes to implement their micro-architecture, to integrate them into an embedded systems, and to efficiently map programs to them. Advanced design tools are required to explore design parameters and establish their relationship to performance, area, and power. That modeling methods and computer-aided tools are keys in development and analysis of reconfigurable computers was recognized already by the pioneers (IEC 61499, 2005. IEC 61131, 2003. R. W. Lewis, 2001). Still, much recently presented reconfigurable architecture has been developed without tools for efficient modeling and analysis of the embedded

Embedded systems are a broad definition of computer systems that are designed for specific tasks. Their architectures are optimized to conform to requirements in their intended application field. In application fields without specific requirements, standard processor systems are used. In contrast, battery operated systems with real-time performance constraints; require customized architectures to achieve the desired performance with constrained power consumption.

With the advent of Field Programmable Logic Devices (FPGA in particular) it became possible to design and implement digital systems without the need for technological steps dealing with silicon. Developing digital devices on the basis of high capacity FPGAs requires using numerous tools, such as FPGA-based boards for rapid prototyping, computer-aided design (CAD) systems, libraries, IP (intellectual property) cores, etc. The study suggests and describes such tools targeted to the design of heterogeneous embedded systems, whose specifications may change continuously (Christensen, 2012. IEC 61131, 2000). The developed tools include: 1. Core Xilinx Spartan 3 FPGA-based prototyping board with an external USB interface. The latter is a removable block, which might be replaced if necessary; 2. Extension boards for connecting typical peripheral equipment and solving application-specific problems, such as implementation of interfaces, communication with standard devices (such as memories), etc.; 3. Software tools for configuring the FPGA, debugging hardware projects, interactions with the board and providing the required experiments 4. Hardware/software tools for data compression and decompression that enable the volume of data transmitted from/to FPGA to be reduced significantly; 5. Hardware/software support for reconfiguration of FPGA-based circuits through reloading reconfiguration bit streams, which have to be preliminary stored in a flash memory available on the board; 6. Hardware/software tools for executing operations over binary/ternary vectors and matrices 7. VHDL templates for interactions with typical peripheral devices, such as an USB controller, a VGA monitor, a static RAM, a keyboard, a mouse, an LCD panel, etc. 8. VHDL templates and IP cores for application specific circuits. Extendable prototyping board - The basic architecture of the board (see fig. 1) has been selected in such a way that allows satisfying the objectives and enabling many design problems from the scope of embedded systems to be solved. Figure 2.1. Basic architecture of the kernel prototyping board.

Reconfigurable architectures (RAs) are devices that contain programmable functional blocks and programmable interconnects between functional blocks, as illustrated in Figure 2. Spatial distribution of functional blocks in conjunction with a flexible interconnect of them, allows exploiting various forms of parallelism inherent in the application. In comparison with the programmability provided by instruction set architectures, the programmability provided by RAs allows substantial changes to the data path itself (OPC UA, 2010). Hence, as with dedicated architectures, RAs can implement application-specific computing structures, but without sacrificing flexibility. That property makes reconfigurable architectures a promising solution to bridge the gap between the programmability of instruction set architectures and the performance of dedicated architectures.

Many emerging applications in the fields of (mobile) communications, computing, and consumer electronics require flexible and evolvable functionalities after the system deployment. In order to offer better computing

number of fixed components, including digital signal processing (DSP) and microprocessor cores, custom hardware, and distributed memory modules (R. Brennan, et. al., 2002. Khalgui, et. al., Aug. 2011). Such reconfigurable architectures, integrated with distributed memory modules, exhibit superior computing capabilities, storage capacities, and flexibility over traditional FPGAs. The successful deployment of these novel embedded systems to the market requires the identification, formalization, and implementation of concepts, methods and tools for their design, considering, together with the traditional requirements, the possibility of dynamically reconfiguring themselves at runtime, over a set of predefined behaviors.

Embedded partial dynamic reconfiguration, due to its internal nature, can be used to realize embedded systems without involving any other device. The successful deployment of such complex and reconfigurable embedded systems to the market requires the identification, formalization, and implementation of concepts, methods, and tools for embedded software design that are able to ease the development of software components and the implementation of the system architecture. In this study we presented an overview on the comprehensive work that has been done in the area of reconfigurable embedded systems, describing both the architectural and the methodological aspects of such systems. Reconfigurable on chip communication platforms are now part of multi-core architectures. Performance improvements can still be achieved working at the bit-stream level with FPGAs or at the instruction level in the case of reconfigurable processors. System level evaluation of reconfigurable platforms is necessary to predict performance, and to find and cure bottlenecks prior to fabrication. A set of flexible transaction level models were developed to allow complete embedded systems with instruction set

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