Study on Hierarchy Representation In Neural Network
Exploring the Challenges and Techniques of Node Extraction in IC Layout Systems
by Jyotsana Goyal*, Dr. Anuj Kumar,
- Published in Journal of Advances in Science and Technology, E-ISSN: 2230-9659
Volume 3, Issue No. 4, Feb 2012, Pages 0 - 0 (0)
Published by: Ignited Minds Journals
ABSTRACT
Before discussing static-analysis tools, it is useful to examine someoperations that simplify the job. In many IC layout systems, the connectivityis not specified, but must be derived from the geometry. Since connectivity iscrucial to most circuit-analysis tools, it must be obtained during or immediatelyafter design. Ideally, network maintenance should be done during design as newgeometry is placed [Kors and Israel], but the more common design system waitsfor a finished layout. The process of converting such a design from puregeometry to connected circuitry is called node extraction. Node extraction of IC layout can be difficult and slow due to thecomplex and often nonobvious interaction between layers. In printed-circuitboards, there is only one type of wire and its interactions are much simpler.This allows PC node extraction to be easily combined with other analysis toolssuch as design-rule checking [Kaplan]. Integrated-circuit node extraction must recognize layer configurationsfor complex components. In MOS layout, for example, the recognition oftransistors involves detection of the intersection of polysilicon anddiffusion, with or without depletion and tub implants, but without contact cutsand buried implants. Rules for detecting such combinations are specially codedfor each design environment and can be applied in two different ways:polygon-based or raster-based. Polygon-based node extraction uses the complexgeometry that is produced by the designer, whereas raster-based node extractionreduces everything to a fine grid of points that is simpler to analyze.
KEYWORD
static-analysis tools, hierarchy representation, neural network, IC layout systems, connectivity, circuit-analysis tools, network maintenance, design system, node extraction, complex and often nonobvious interaction, printed-circuit boards, design-rule checking, integrated-circuit node extraction, layer configurations, MOS layout, transistors, polygons, rasters, design environment, fine grid of points
INTRODUCTION
The first aspect of neural network design that must be represented is hierarchy. Hierarchical layouts have entire collections of circuit objects encapsulated in a cell definition. Instances of these cells then appear in other cells, which mean that their entire contents exist at each appearance. The representation of cell instances can be done with instance objects. These objects, which point to their cell definitions, are actually complex components, as opposed to primitive components such as the NAND gate. Complex components can use the same object structure as primitive components use, but their prototype objects have different attributes. For example, a primitive prototype may have attributes that describe it graphically, whereas a complex prototype will contain a list head that identifies the sub objects inside the cell. Although it is tempting to create a new object type so that design can be done with components and instances, the representation is much cleaner if only components are used because then there are fewer database objects and they can be treated uniformly. Given this uniform representation of hierarchy, every cell is a component prototype. In Fig.1, the design of Fig.is shown in its proper perspective as a complex prototype called "Bignothing." Note that the "Out" connection on the rightmost inverter component in "Bignothing" is exported and called "Final." Other cells may contain instances of the "Bignothing" cell, thus including its contents. The "Something" cell in Fig. 2.8(c) has two components: one that is a primitive component and one that has a complex
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prototype. The complete layout is shown at the bottom of the figure. FIGURE 1 Hierarchy: (a) Complex prototype for "Bignothing" (b) Primitive prototypes (c) Complex prototype for "Something" (d) Represented layout.
REVIEW OF LITERATURE
Because complex component prototypes are objects, the question of where to store their subobject list heads is resolved. These pointers are simply attributes in the complex-component prototype objects. However, a new issue is raised: how to represent the lists of component prototypes. To do this, two new object types must exist: the environment and the library. The environment is a collection of primitive-component prototypes, organized to form a design environment such as is discussed in Thesis . A library is a collection of complex component prototypes, or cells, presumably forming a consistent design. A good design system allows a number of different environments and permits multiple libraries to be manipulated. Figure 2 shows an overall view of the objects in such a design system. Environments provide the building blocks, which are composed into cells. Cells are then hierarchically placed in other cells, all of which are represented in libraries. A collection of library objects therefore contains everything of value in a particular design. Although libraries provide convenient ways to aggregate collections of cells, a further level of abstraction may be used to aggregate libraries by designer. In multiperson designs, a project can be defined to be a collection of works from many people [Clark and Zippel]. Subprojects identify the work of individuals and eventually arrive at libraries and cells to describe the actual design. Thus hierarchy can be used to describe both circuit organizations and human organizations.
Figure 2 Environments and libraries: (a) Environments (b) Libraries.
MATERIAL AND METHOD
The raster method of node extraction views a layout as a unit grid of points, each of which is completely filled with zero or more layers [Baker and Terman]. Such a view is called a raster image since it changes the layout into a form that can be scanned in a regular and rectangular manner. Analysis is done in this raster scan order by passing a window over the image and examining the window's contents (see Fig. 3). As the window is moved, the lower-right corner is always positioned over a new element of the design. This element is assigned a node number based on the contents and node numbers of the other elements in the window. In fact, since this method is valid only for Manhattan geometry, the window need be only 2 × 2 because there are only two other elements of importance in this window: the element above and the element to the left of the new point.
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FIGURE .3 Raster-based circuit analysis: (a) First position of window (b) Second position of window (c) Raster order. Rules for assigning node numbers are very simple (see Fig. 2.9). If the new point in the lower-right corner is not connected to its adjoining points, it is given a new node number because it is on the upper-left corner of a new net. If the new point connects to one of its neighbors, then it is a downward or rightward continuation of that net and is given the same node number. If both neighbors connect to the new point and have the same node number, then this is again a continuation of a path. However, if the new point connects to both neighbors, and they have different node numbers, then this point is connecting two nets. It must be assigned a new node number and all three nets must be combined. Node-number combination is accomplished by having a table of equivalences in which each entry contains a true node number. The table must be as large as the maximum number of different net pieces that will be encountered, which can be much larger than the actual number of nets in the layout. Special care must be taken to ensure that transistor configurations and other special layer combinations are handled correctly in terms of net change and connectivity. FIGURE 4 Raster-based node extraction: (a) Upper-right and lower-left quadrants have any node number, ?; lower-right not connected to either neighbor; lower-right assigned new node number, B (b) One corner (upper-right or lower-left) has node number, A, and is connected to lower-right corner; lower-right assigned same node number, A (c) Upper-right and lower-left have same node number, A; both corners connected to lower-right; lower-right assigned same node number, A (d) Upper-right and lower-left have different node numbers, A and B; both corners connected to lower-right; lower-right assigned new node number, C and adjoining nodes (A and B) are marked the same as C.
CONCLUSION
When the entire layout has been scanned, an array of node numbers is available that can be used to tell which two points are connected. It is necessary to walk recursively through this table when determining true node numbers since a net may be equivalenced multiple times. Nevertheless, this information is easily converted to a netlist that shows components and their connections.
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