Design and Implementation of Image Processing on Epga

Nowadays, the importance of image processing is rapidly increasing in such fields as industrial automation, security, health, and traffic control in parallel with the developments in technology. The most challenging difficulty in applications used in these fields is to make system run real-time (Russ, 2011). It is not always possible to make the system run real-time by the use of software used on a general purpose computer since the resources of memory, CPU and peripheral devices in computers are limited. In most image processing applications, dozens of operations are performed on each pixel. That these operations are performed by general purpose processors sequentially leads to negative consequences in terms of both resource consumption and performance (Samarawickrama, et. al., 2010). However, EPGAs has the capability to operate in a parallel way in terms of hardware, which distinguishes them from traditional processors. In this way, operations are divided into pieces in EPGAs and multiple operations can be done simultaneously. Image and video processing are an ever expanding and dynamic areas with applications reaching out into our everyday life such as in medicine, astronomy, ultrasonic imaging, remote sensing, space exploration, surveillance, authentication, automated industry inspection and in many more areas (Russ, 2011). Reconfigurable hardware in the form of (EPGAs) offers many performance and implementation benefits for executing video processing applications. EPGAs generally consist of logical blocks and some amount of Random Access Memory (RAM), all of which are wired by a vast array of interconnects. All logic in EPGA can be rewired, or reconfigured with different purposes as many times as a designer likes. One of the benefits of EPGA is its ability to execute operations in parallel, resulting in remarkable improvement in efficiency. The main advantage of EPGA-based design is the flexibility to exploit the inherently parallel nature of many image processing problems (Samarawickrama, et. al., 2010).

The difficulty of generating a design from a set of requirements and specifications increases as the and verification (Moertti, 2002). which is an algorithm modeling methodology that focuses on a higher abstraction level using high-level languages such as C, C++, or MATLAB to model the entire behavior of the system with no initial link to its implementation. The ESL design and verification enables embedded system design, verification, and debugging for designing hardware and software implementation of custom system-on-EPGA (Akpan, 2012). The Xilinx AccelDSP tool (Ahmad, et. al., 2010) is an advanced ESL design tool which transforms a MATLAB floating-point design into a hardware module that can be implemented in EPGA. The AccelDSP Synthesis Tool features an easy-to-use Graphical User Interface that controls an integrated environment with other design tools such as MATLAB, Xilinx ISE tools, and other industry standard HDL simulators and logic synthesizers. This paper presents the design and implementation of EPGA-based architecture for image processing by employing Xilinx AccelDSP tool. This tool has been selected, since it can converts automatically from high-level languages (HLLs) to register transfer level (RTL) HDL and even directly to EPGA configuration bit stream (Yu, et. al., 2008).

The integration of Simulink and MATLAB from The Math Works (Sima, et. al., 2003) and the EPGA design suite of tools (Jack, 2007) now allow embedded system development from a model-based view point which targets an EPGA. The AccelDSP software (Ahmad, et. al., 2010) is the Mat lab signal processing model synthesis tool from Xilinx, which allows an algorithm developer to transform a Mat lab floating-point design into a hardware module that can be implemented in silicon. Its most interesting feature is that a synthesizable RTL HDL model and a Test bench can be achieved to ensure bit-true, cycle-accurate design verification. The tool also provides scripts that invoke and control downstream tools such as HDL simulators, RTL logic synthesizers and implementation tools. Three AccelDSP implementation options (flows) are available as illustrated in “Fig.1”. The default synthesis flow is called the ISE Synthesis Flow where the main objective is to create an implementation using ISE software and verify the design using HDL gate-level simulation (Jack, 2007. ITU-R, 2000. Saidani, et. al., 2009). The second flow is called the System Generator flow. In this flow, an IP core is created for exporting and integrating with a larger System Generator design. The third flow, HW Co-Sim, is similar to the ISE flow but the objective is to simulate the design in hardware platform like a Virtex-4, a Virtex-5, or a Spartan-3A DSP Platform. Not only does the simulation run much faster, but this flow proves that the design will run in the target hardware. The AccelDSP IP Core Generators provide a direct path to hardware implementation for complex MATLAB built-in and toolbox functions, which when used with the and facilitate algorithmic synthesis for EPGAs (Akpan, 2012).

The Zed Board Zynq-7000 EPGA development kit (Jack, 2007) was used in this study. Zynq-7000 is different from standard EPGAs in that it contains Artix-7 EPGA and ARM Cortex-A9 processor on the same chip together. In EPGA card having this

containing computations can be done on the processor by using software. The internal structure of Zynq is shown in Fig. 2. Zynq consists of two parts: Processing System and Programmable Logic. Processing System (PS) works like a traditional processor since it contains structures such as ARM Cortex-A9, Floating Point Unit, Memory Controller, Gigabit Ethernet Controller and USB Controller. Programmable Logic part, on the other hand, contains all the structures of a standard EPGA (Sapkal, et. al., 2008. Canny, 1986. Behera, et. al., 2012. Abbasi and Abbasi). The communication between PS and PL parts is provided by high performance data-paths.

The developed system consists of two parts: hardware and software. The software performs the operation of image capturing from the video source and transferring it to the hardware part. Any image source that can run on Linux (such as USB camera, network video stream, video file etc.) can be used in the software. In the hardware part, image processing algorithms are implemented. The schema of the general system formed by the co-use of software and hardware parts is shown in Fig. 3.

In the system, video frame is firstly obtained from the video source via software and operating system. Then, the software transfers the parts to be processed on the video frame to the temporary image memory on the EPGA. The transfer of operation, on the hardware part, is controlled by Temporary Image Memory Controller (TIMC) module. The video is transferred to Temporary Image Memory (TIM) module via the TIMC. The processed and unprocessed forms of the image can be stored in the TIM module. Image Processing Co-processor (IPC) module performs image processing algorithms. The IPC module performs the image processing operations by fetching the pixels from TIM module and storing the processed forms of the pixels. These modules are explained in the 4th part. After the operations on the image are completed on the hardware part, the status notification is transmitted to the software. After this step, the processed image can be read via the software part if needed. The original and processed forms of the image are shown on the monitor by using the HDMI output of EPGA kit.

Two image processing applications have been designed and developed using Xilinx AccelDSP. A Color space conversion RGB to YCbCr and Sobel edge detector have been designed and implemented on EPGA.

A color space is a mathematical representation of a set of colors. The three most popular color models color printing).However, none of these color spaces are directly related to the intuitive notions of hue, saturation, and brightness. All of the color spaces can be derived from the RGB information supplied by devices such as cameras and scanners (Saidani, et. al., 2009). “Fig.4” shows the basic steps in the AccelDSP Synthesis Flow (System Generator implementation option) with output results for the floating point and fixed point model respectively and the System Generator CSC IP Core generated.

The IP Core block generated is exported and integrated with a larger System Generator design for hardware Co-simulation and implementation. “Fig.5” shows the design that uses the generated IP Core module and Xilinx block sets for RGB to YCbCr conversion. The hardware Co-simulation results for the CSC design for the input image are shown in “Fig.4”

From the development of EPGA technology, the methodology challenges the update of various EDA tools. Based on the standard development flow, initial efforts have been transferred to high-level design and synthesis. There are many conversion tools such as C- AccelDSP-to-EPGA (Ahmad, et. al., 2010) flow can be discussed as follows.  Fast time-to-market for computer vision algorithms development. It could be described as a timely, advantageous option for developing in a much more comfortable way than that permitted by VHDL or Verilog hardware description languages (HDLs).  Friendly graphical user interface (GUI) that features a Design Flow Manager to guide the designer quickly through the design transformation steps. The GUI also features a Project Explorer window that lets the designer graphically browse the design hierarchy and view the M-files and the generated HDL source files.

 AccelDSP is capable of generating a System Generator Block that can be used in a larger design. With the assistance of specified DSP blocks for EPGA, a design in Xilinx System generator can greatly shorten the development cycle from algorithm to hardware. An important attribute of our design using AccelDSP was that the block sets generated in AccelDSP for Xilinx System Generator, are reusable and can be neatly divided into appropriate libraries each containing blocks specific to a certain field such as (for example) Image Processing Library (Gribbon, et. al., 2006). The EPGA design made using high-level synthesis (HLS) tool needed much less effort than the

AccelDSP is its automated and flexible floating-to-fixed-point conversion.

Implementation of a video processing algorithm on the EPGA is complex, tedious and error prone when using traditional design methodologies. Since time-to-market is very important, it is required to look at the product development cycle to reduce the design time and gain a competitive edge in the time to-market. Therefore, the adoption of high-level synthesis (HLS) tools is now getting into EPGA based designing. To ease the process of transforming a MATLAB floating point design into a hardware module, Xilinx introduced the AccelDSP software for rapid prototyping of an algorithm in MATLAB into hardware. In this paper, a Xilinx AccelDSP based approach is presented for image processing applications to minimize the time to market factor. A Color space conversion (CSC) RGB to YCbCr and Sobel edge detector have been designed and implemented on EPGA. The designs were implemented on Spartan 3A DSP and Vertex 5 devices and their utilization summaries are compared.

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