The Triptych Fpga Architecture

Enhancing Flexibility and Performance through FPGA Architecture

by Sunita Rani*,

- Published in Journal of Advances in Science and Technology, E-ISSN: 2230-9659

Volume 4, Issue No. 7, Nov 2012, Pages 0 - 0 (0)

Published by: Ignited Minds Journals


ABSTRACT

Field-programmable gate arrays (FPGAs) have quicklybecome an important medium for the implementation of digital logic. Thesearrays exploit the increasing capacity of integrated circuits to providedesigners with reconfigurable logic that can be programmed on anapplication-specific basis. This drastically increases flexibility in both thedesign process and the final artifact by permitting one board-level design toperform many functions, or to be upgraded in the field.

KEYWORD

Field-programmable gate arrays, FPGAs, digital logic, reconfigurable logic, application-specific basis, flexibility, design process, final artifact, board-level design, upgrade

[2] Atmel “Configurable Logic Design and Application Handbook” , 1995. [3] Black, P, Meng. T., “A 140 mb/s 32 State, Radix 4 Viterbi Decoder,” IEEE Journal of Solid State Circuits Vol. 27, No. 12, December 1992, pp. 1877-1885. [4] Bowhill, W., et al, “A 433 MHz 64b Quad Issue RISC Microprocessor,” IEEE Journal of Solid State Circuits, Vol 31, No. 11, November 1996, pp ##. [5] Brebner, G. , “Configurable Array Logic Circuits for Computing Network Error Detection Codes,” Journal of VLSI Signal Processing, 6, 1993, pp. 101-117. [6] Chandrakasan, A. , “Low Power Digital CMOS Design,” PhD. Thesis, U.C. Berkeley, August 1994. [7] CLAy Family Introduction Datasheet, National Semiconductor, June 1994. [8] DeHon, A. , “Reconfigurable Architectures for General Purpose Computing,” M.I.T. PhD Thesis, A.I. Technical Report 1586, October 1996. [9] Dobbelaere, I. , Horowitz, M. , Gamal, A. , “Regenerative Feedback Repeaters for Programmable Interconnections”, ISSSC Digest of Technical Sections 1995, p.116- 117. [10] Farrhi, A. , Sarrafzadeh, M. , “FPGA Technology Mapping for Power Minimization,” International Workshop on Field-Programmable Logic and Applications, FPL ‘94. Proceedings, Springer-Verlag, 1994. p. 66-77. [11] Gamal, A. , et al., “An Architecture for Electrically Configurable Gate Arrays,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, pp 394-398. [12] George, V. , The Effect of Logic Block Granularity on Interconnect power in a Reconfigurable Logic Array”, CS 294 report, May 1997. [13] Goto, G., et al “A 4.1ns Compact 54x54 Multiplier Utilizing Sign-Select Booth Encoders,” IEEE Journal of Solid State Circuits, Vol 32, No. 11, November 1997, pp 1676-1683. [14] Hauck, S., Borriello, G., Ebeling, C. , “Triptych: An FPGA Architecture with Integrated Logic and Routing”, in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, pp. 26-43, March 1992. [15] Infopad Project, U.C. Berkeley, http://infopad.EECS.Berkeley.EDU/infopad [16] Izumikawa, M. , et al., “A 0.25um CMOS 0.9v 100-MHz DSP Core,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 1, January 1997, p. 52-60. [17] Jou, S., et al, “A Pipelined Multiply-Accumulator using a High-Speed Low-Power Static and Dynamic Full Adder Design,” IEEE Journal of Solid State Circuits, Vol 32, No. 11, November 1997, pp ##. [18] Kaushik, R., Prasad, S., “FPGA Technology Mapping for Power Minimization,” International Workshop on Field-Programmable Logic and Applications, FPL ‘94. Proceedings, Springer-Verlag, 1994. p. 57-65.