The signals in the real world are analog in nature, for example light, sound, video etc. Since digital circuits are more robust, transmission errors are less, offer greater advantages over analog circuits in processing speed and are more efficient. Hence it is always better to process and transmit the information in digital form and finally it can be converted to analog form. So, in order to obtain digital signal, we need to make use of Analog-to-Digital converters and whenever, we need the analog signal back then digital-to analog converters are required. The data converter applications range from audio communication to medical field. These converters are implemented using a variety of architectures. The ADC is characterized by three factors namely speed, area and power consumption. The flash ADC is the fastest one among all ADCs because of its parallel operation. This is suitable for applications requiring very large bandwidths. This paper presents systematic design of 3-bit flash ADC implemented in 180nm CMOS technology. This work includes the design of high speed flash ADC with an encoder with less number of transistors. This paper is organized as follows. Section II describes the system architecture and deals with the design of building blocks. Section III briefly covers simulation results.

Figure1 shows the typical flash ADC [1] block diagram. It has resistive a ladder network to generate the internal reference voltages for the comparators. The number of resistors is 2N and comparators required are 2N -1 for N bit ADC. The comparators output is thermometer code which is converted to the digital form by an encoder designed with full adder circuits.

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The reference voltages are generated with a resistor ladder in which each resistance is of same value. For n bit converter 2N are required. We have used poly resistors to build the resistor array. The resistor value is calculated by,

The VLSB indicates the difference between adjacent reference voltages. Which have to be applied to the comparator arrary.

Comparator is critical part of the ADC design. Here we use two staged op amp in designing the comparator circuit. Below Figure 2 shows the structure of two stage op amp comparator.

First stage is a differential amplifier to reduce the noise and second stage is common source amplifier to have higher gain. The biasing technique is of current mirror type.

Encoder is the digital part of the ADC which converts thermometer coded input signal to the normal digital output. For 3-bit FADC the thermometer code is of 7 bit, the outputs of the comparators as indicated in below table.

In this paper the encoder circuit is designed using cascading of full adders. Each of the adder schematic uses 10 Transistors. This circuit is designed using XOR and XNOR logic.

For the designed 3-bit ADC we need four full adder circuits and three delay circuits to apply the inputs simultaneously. Figure 4 below the shows the encoder schematic diagram.

S. S. Kamate1*, Akshata Naikar2, S. S. Malaj3 2

flash ADC.

The schematic and layout of the designed 3-bit flash ADC are simulated using cadence 180nm technology with Virtuoso analog design environment. 3-bit Flash ADC in 180nm technology using Virtuoso analog environment design of cadence tools. Pre-layout and Post layout simulation results.

1. Comparator output waveform As shown in below Figure 6, a sinusoidal wave is applied to the noninverting terminal of the comparator and reference signal is applied to the inverting terminal. The resulting output of the comparator goes high when the input voltage at the noninverting terminal surpasses the reference voltage applied at the inverting terminal.

As the encoder uses 10T full adders below Figure 7 shows the output of 10T full adder and the Figure 8 represents the output of encoder

B. Post layout simulation results 1. Layout of Comparator

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3. Layout of ADC The Figure 11 shows simplified layout of complete 3-bit Flash type ADC. It includes resistive ladder network designed with poly layers, to generate the seven required reference voltages.

These seven voltages are applied at the inverting terminals of the comparators. The input is applied at the noninverting terminal of all the comparator circuits. Depending upon the applied input voltage the comparators produce “high” or “low” output. The seven comparators output forms the thermometer code, is applied to the full adder circuits in desired fashion to have an encoder operation to get the required digital output

This paper presented systematic design of 3-bit Flash ADC. This architecture is simulated in cadence analog design environment using gpdk 180nm technology with power supply of 5V. The authors thank the entire team of Electronics and Communication Department, the management of Hirasugar Institute of Technology Niadasoshi for their kind support and cooperation.

Yatish Lavaniai, George Tom Varghese and K. K. Mahapatra “An Ultra Low Power Encoder for 5 Bit Flash ADC” pp. 978-1-4673-5301-4/13, 2013 IEEE. Pradeep Kumar, Amit Kolhe, “Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS” International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue 5, November 2011. Sarojini Mandal, Dr.J.K Das “DESIGN OF 3-BIT LOW POWER FLASH TYPE ADC” International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 4, April 2014. Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov, “A 4-Bit 5GS/s Flash A/D Converter in 0.18μm CMOS”, pp. 0-7803-8834-8/05, 2005, IEEE. Sujata S Kamate received her Bachelor of Engineering degree in Electronics and Communication Engineering from the HIT, Nidasoshi, M.Tech in Digital Electronics from GIT, Belagavi. Presently working as Assistant Professor in HIT, Nidasoshi. Her technical interests include Data Conversion and CMOS VLSI Design.

Student, ECE Department, HIT, Nidasoshi