Design of High Speed Hardware Efficient Modified Booth Multiplier Using HDL

Low power consumption in CMOS circuits is the present research as high integration causes increases the power dissipation. Modified Booth Encoders attract much attention because of low power dissipation and high throughput. The advantages of the Modified Booth Algorithm are the operation speed and the power dissipation. The AND array method and the Booth encoding method are algorithms for partial product generation. The reduction of partial products is required for higher-bit multiplication, because the addition of partial products stage occupies a large circuit area and causes huge delay. In general, a multiplier uses Booth encoder and array of full adders (FAs), or CLA tree instead of the array of FAs. This multiplier mainly consists of the three parts: Booth encoder, a tree to compress the partial products such as CLA tree, and final stage adder. CLA tree is to add the partial products from encoder as parallel as possible. In real implementation, many (4:2) compressors are used to reduce the number of outputs in each pipeline step. The most effective way to increase the speed of a multiplier is to reduce the number of the partial products because multiplication precedes a series of additions for the partial products. To reduce the number of calculation steps for the partial products, Modified Booth Encoder has been applied mostly where CLA tree has taken the role of increasing the speed to add the partial products. The AND array method and the Booth encoding method are algorithms for partial product generation. The reduction of partial products is required for higher-bit multiplication, because the addition of partial products stage occupies a large circuit area. In this brief, we present a design technique that improves speed of Modified Booth Multiplier without a power penalty. Based on the proposed technique, the maximum speed of Modified Booth Multiplier can be increased by a great factor comparing with Booth Multiplier.

A modification of the Booth algorithm was proposed by Mac-Sorley in which a triplet of bits is scanned instead of two bits. This technique has he advantage of reducing the number of partial products by one half regardless of the inputs. B. Modified Booth Algorithm The multiplier has a 8-stage structure where the PPG block, the PPA block and the FSA block consist of 2 stages, 1 stage and 5 stages respectively.

When the number of partial products is reduced to sum and carry words, a final adder is required to generate the multiplication result. The number of bits of the final adder is the sum of the number of bits of the multiplier and multiplicand. Thus, the data path width is usually doubled and the delay of this stage is most severe. Normally 6-bit CLAs can be used to reduce the delay and area requirements. This adder is a practical design with reduced delay at the price of more complex hardware.

Multiplication consists of three steps: 1) the first step to generate the partial products; 2) the second step to add the generated partial products until the last two rows are remained; 3) the third step to compute the final multiplication results by adding the last two rows. The modified Booth algorithm reduces the number of partial products by half in the first step. This project has used the modified Booth encoding (MBE) scheme proposed in [2]. It is known as the most efficient Booth encoding and decoding scheme. To multiply X by Y using the modified Booth algorithm starts from grouping Y by three bits and encoding into one of {-2, -1, 0, 1, 2}. Table I shows the rules for obtaining the product. It is possible to reduce the number of partial products by half, by using the technique of radix 4 Booth recoding. The basic idea is that, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, we only take every second column, and multiply by ±1, ±2, or 0, to obtain the same results. Multiplication involves the generation of partial product, one of the each digit in the multiplier. These partial products are then summed to produce the final product. The partial products are easily defined. When the multiplier bit is 0, the partial product is 0. When the multiplier is 1, the partial product is the multiplicand. The total product is produced by summi.ng the partial products. For this operation, each successive partial product is shifted one position to the left relative to the preceding partial product. The multiplication of two n-bit binary integers, results in a product of up to 2^n bits in length.

Comparison of Time Delay for Booth and Modified Booth Multiplier

By observing above comparison it is clear that Modified Booth Multiplier takes less time for calculation than that of Booth Multiplier for 8-bit, 16-bit, 32-bit and 64-bit. So Modified Booth Multipliers are more efficient compared to Booth Multiplier.

The 64- bit multiplication is executed successfully and got the correct results. The project has reduced the number of partial products considerably, and increased the speed of execution. The program has given correct results for number of times. The project code is much efficient in terms of number of bits and in reducing the amount complexity accomplished. This project can be further modified to obtain the results for the numbers with the numbers of bits greater than 64. They can also be used for designing SFQ logic circuits.

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