Design of High Speed Hardware Efficient Modified Booth Multiplier Using HDL

Efficiency Analysis of Hardware Efficient Modified Booth Multiplier

Authors

  • Nyamatulla Patel Dept. of ECE, HIT Nidasoshi Author
  • Vidyashri M. Bastawadi Dept. of ECE, HIT Nidasoshi Author
  • Suparna R. Daddimani Dept. of ECE, HIT Nidasoshi Author

Keywords:

high speed, hardware efficient, modified booth multiplier, HDL, 2-bit Booth encoder, Josephson Transmission Lines, Passive Transmission Lines, Booth encoding method, partial products, AND array method

Abstract

A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method. The proposed 64-bit modified booth encoders are designed using Modified Booth Algorithm and Carry Look Ahead Adder. The efficiency of this project is verified by successive execution with different inputs.

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Published

2017-06-01

Issue

Vol. 14 No. 1 (2017): Journal of Advances in Science and Technology (JAST)

Section

Articles