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Authors

C. Aruna Bala

Abstract

The paper describes design requirements of a basic stage (called MDAC- Multiplying Digital-to-Analog Converter) of a pipelined ADC. There existerror sources such as finite DC gain of opamp, capacitor mismatch, thermalnoise, etc., arising when the switched capacitor (SC) technique and CMOStechnology are used. These non-idealities are explained and their influences onoverall parameters of a pipelined ADC are studied. This paper provides ageneral background for the work carried out in this book. Therefore, itspurpose is to cover all aspects of the developed work. First, some A/Dconverter (ADC) architectures will be briefly described. The common element ofthese architectures is the use of the multiplying-DAC (MDAC) circuit as theirprincipal block. Advantages and limitations of the architectures will also begiven. The MDAC circuit is one of the key elements of this book. Given thatthis work presents a prototype of a pipeline ADC, it is important to describeeach of its building blocks. Besides detailing the function and importance ofeach block, related errors and performance limiting aspects will also be given.After the description of the pipeline converter sub-blocks, various static anddynamic performance parameters, and metrics that characterise ADCs are given.It will be the objective here to explain the parameters that fundamentally dictatethe performance of ADCs.

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