An Efficient N Bit Multiplier Design Based on Vedic Mathematics

Enhancing Signal and Image Processing with Vedic Mathematics

Abstract

In this paper, a high speed N bit multiplier based on Vedic mathematics “Urdhva Tiryakbhyam” is proposed. in order to decrease the delay and power consumption in the processing of the signals in the system. The most significant aspect of the proposed method is that, the multiplier design is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics .It generates all partial products and their sum in one step. The delay of proposed multiplier is compared with Array multiplier. The synthesis results show that, the N bit multiplier based on Vedic mathematics “Urdhva Tiryakbhyam” has a less delay compared to the array multiplier. The results indicates that the N bit multiplier based on Vedic mathematics “ Urdhva Tiryakbhyam” has great impact on improving the speed of signals in the field of signal and image processing.