High Speed Area Efficient 32 Bit Wallace Tree Multiplier: Design and Implementation of a High Speed Area Efficient 32 Bit Wallace Tree Multiplier

Abstract

A 32 bit high speed Wallace tree multiplier is designed using Verilog HDL and 4 bit multiplication is implemented in FPGA. The circuit is designed using carry save adder architecture and finally with one look ahead carry adder. The design is an improved version of tree based Wallace tree multiplier architecture. The proposed method aims at high speed multiplication of 32 bit Wallace tree multiplier. The entire design of 4 bit multiplication is coded in Verilog HDL, simulated with Modelsim and synthesized using Xilinx FPGA device and the similar algorithm is used for computing 32 bit multiplication. The result shows that the proposed architecture takes very less time for computing the multiplication of two 32 bit numbers. The proposed multiplier is much efficient than the existing methods.